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VHDL
Hexadecimal value (literal) as function parameter, is it possible?
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[QUOTE="wimille, post: 5087606"] Hi, I'm currently writting a package file for my design and my testbenchs, and i need to write a function to resize an vector. I write the function as follows: function resize ( vec : in std_logic_vector; size : in natural) return std_logic_vector is variable resized : std_logic_vector( size-1 downto 0) := (others => '0'); variable len : natural := 0; begin len := vec'length; if ( len = size ) then resized := vec; elsif ( len > size ) then resized := vec(size-1 downto 0); elsif ( len < size ) then resized := resized(size-1 downto len) & vec; end if; return resized; end function resize; But i need to update or to overload this function in order to allow this type of operation: toto <= resize( x"AAAA", 10); Because if i write this now, i've got this error in Modelsim: # ** Fatal: (vsim-3607) Slice range direction (downto) does not match slice prefix direction (to). Thanks for your help [/QUOTE]
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Hexadecimal value (literal) as function parameter, is it possible?
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