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Message: [QUOTE="Andy, post: 5087997"] I agree with Nicolas. This is sometimes called "range normalization", and if you look at the reference implementations of IEEE packages, it is very commonly used. To add to what Kevin said, if your tools support VHDL-2008, you can use the ieee.numeric_std_unsigned package; it defines resize() for std_logic_vectors. Numeric_std_unsigned applies numeric_std's functions and operators for the unsigned type, to std_logic_vector. It also defines a to_std_logic_vector(natural) and similar aliases to_stdlogicvector(), to_slv(), etc. Numeric_std_unsigned is similar in concept to the debunked "std_logic_arith" package, but is official and governed by the standard, ensuring compatibility across tool vendors. If your tools do not support VHDL-2008, call the vendor and complain. Loudly. Andy [/QUOTE]