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Message: [QUOTE="Mike Treseler, post: 1905766"] no A synchronous "latch" is a d-flop. Once you fix the syntax errors, your example would latch low forever when A goes high. But since an fpga registers start low on configuration, synthesis would likely just wire B to ground for you. A more interesting example would give the output some way to recover. For a synchronous design, think about how you want your registers to initialize and update Describe that exactly, and don't worry about what synthesis will do. -- Mike Treseler ____________________________ library ieee; use ieee.std_logic_1164.all; entity no_else is port (a, clk : in std_ulogic; b : out std_ulogic); end no_else; architecture sim of no_else is begin process(clk) is begin ck : if (rising_edge(clk)) then b <= a; if (a = '1') then b <= '1'; end if; end if ck; end process; end architecture; [/QUOTE]