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Question on Comparing two std logic vecter
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[QUOTE="Tha, post: 4201411, member: 72828"] Okay, just after I post this thread , I found out why my code doesn't work. "Note that this library doesn't allow you to do comparisons on std_logic_vector values. That's because it's impossible for it to determine whether a particular std_logic_vector is representing a signed or unsigned value. To do this, you need to use either the std_logic_unsigned or std_logic_signed libraries." referred from [URL]http://www.cs.sfu.ca/~ggbaker/reference/std_logic/arith/comp.html[/URL] [/QUOTE]
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