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[QUOTE="Roya, post: 3908383, member: 59024"]
I understood that these simultaneous assignments are not possible so i try another way: I make the clk, 3 times faster .so when rising edge of the faster clk is comming for the third time , all the signals Red,Blue and Green are initialized and all of them are prepared , at this time the sysclk goes to the rising edge mode so the other modules start their works as before with the frequency  27 Mhz.
am i right?
but i face this error --> "ERROR:Xst:841:"bad condition in wait statement, or only one clock per process." 
because of this part of my code in my top module during the post-route simulation:
 ***********in my top module:**************
sysclkGenerator:process
    begin
        sysclk<='0';
        for count in 1 to 3 loop
           wait until clk'event and clk ='1';
        end loop;
        sysclk <= '1';
      wait;   
    end process sysclkGenerator;

*******************************************

*****************in my testbench :*****************

clk<=not(clk) after 3.08 ns ;

*****************************************************

actualy the frequency of sysclk should be 27 Mhz, means 18.5 ns one and 18.5 ns zero, so sysclk is  6*3.08=18.5
[/QUOTE]

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