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VHDL
So, they started synthesizing shared variables?
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[QUOTE="Dave Farrance, post: 3873616"] Maybe the synthesiser has grouped the processes together because they are both triggered on the same rising_edge(clk), making C absorb unambiguously into q_b? I don't know how other synthesisers would handle it. [/QUOTE]
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So, they started synthesizing shared variables?
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