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VHDL
So, they started synthesizing shared variables?
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[QUOTE="Tricky, post: 3873618"] If it did that then the same would apply if C was a signal - when C is declared as a signal, it throws an error saying multiple constant drivers on C. If it combined the 2 processes, it wouldnt complain and just take the last assignment to C. [/QUOTE]
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So, they started synthesizing shared variables?
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