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VHDL
So, they started synthesizing shared variables?
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[QUOTE="Dave Farrance, post: 3873660"] I see. The shared variable assignments are computed sequentially within the scope of the shared variable, so I guess that the behaviour that you describe would be correct for simulation. I agree that allowing synthesis, just because it can in this case, is very questionable. [/QUOTE]
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So, they started synthesizing shared variables?
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