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VHDL
So, they started synthesizing shared variables?
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[QUOTE="HT-Lab, post: 3876792"] mmmm, not sure which version of Modelsim you are using but my 6.5b version complained bitterly and told me to get some more coffee.. After some quick hacking I changed the code into: type ram_t is protected -- Error in PS impure function read(a : natural) return std_logic_vector; procedure write(a : natural; d : std_logic_vector); end protected ram_t; type ram_t is protected body type ram_array_t is array(0 to 127) of std_logic_vector(7 downto 0); variable ram_array : ram_array_t; impure function read(a : natural) return std_logic_vector is begin return ram_array(a); end function read; procedure write(a : natural; d : std_logic_vector) is begin ram_array(a) := d; end procedure write; end protected body ram_t; Unfortunately it didn't go through Precision although this might be due to me screwing up the code. [40000]: vhdlorder, Release 2009a.15 [40000]: Syntax error at or near "protected" [40000]: VHDL file ordering failed. Hans [URL="http://www.ht-lab.com"]www.ht-lab.com[/URL] [/QUOTE]
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So, they started synthesizing shared variables?
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