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VHDL
String to std_logic_vector
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[QUOTE="Shannon, post: 3556124"] As I suspected. So to flesh things out a bit.... function Version_Char_To_slv(Some_Char: character) return slv is variable Return_Value: slv(7 downto 0) := (others => 0); begin case Some_Char is when "0" => Return_Value := STD_LOGIC_VECTOR(TO_UNSIGNED(0,8); when "1" => Return_Value := STD_LOGIC_VECTOR(TO_UNSIGNED(1,8); ... when "a" => Return_Value := STD_LOGIC_VECTOR(TO_UNSIGNED(97,8); ... when "-" => Return_Value := STD_LOGIC_VECTOR(TO_UNSIGNED(45,8); ... when others => null; end case; return(Return_Value); end function Version_Char_To_slv; and then back in my main process.... for i in 1 upto 16 loop regs(i) <= Version_Char_To_slv(ver(i)); end loop; Or something like that? [/QUOTE]
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VHDL
String to std_logic_vector
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