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VHDL
String to std_logic_vector
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[QUOTE="Mike Treseler, post: 3556141"] -- or this: type char2std_t is array(character) of std_ulogic; constant char2std_c : char2std_t := ( 'U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z', 'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-', others => 'X'); function str2std(arg : string) return std_logic_vector is variable result : std_logic_vector(arg'length - 1 downto 0); variable j : integer; begin j := arg'length -1; for i in arg'range loop result(j) := char2std_c(arg(i)); j := j -1; end loop; return result; end function; -- Mike Treseler [/QUOTE]
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