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[QUOTE="Shannon, post: 3521802"]
Ok, here is the relevant code snipits:

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;

HWID	: INOUT	STD_LOGIC_VECTOR(7 DOWNTO 0);
RAM_addr	: OUT	UNSIGNED(9 DOWNTO 0);

TYPE reg_type IS ARRAY (0 TO NUM_REGS-1) OF
STD_LOGIC_VECTOR(HWID'RANGE);
SIGNAL	regs	: reg_type;
SIGNAL	data_in	: STD_LOGIC_VECTOR(HWID'RANGE);

Line 156: 	RAM_addr <= UNSIGNED("00" & data_in);

and the error is:

Error (10327): VHDL error at xFace.vhd(156): can't determine
definition of operator ""&"" -- found 2 possible definitions
Error (10647): VHDL type inferencing error at xFace.vhd(156): type of
expression is ambiguous - "reg_type" or "std_logic_vector" are two
possible matches
Error (10411): VHDL Type Conversion error at xFace.vhd(156): can't
determine type of object or expression near text or symbol "UNSIGNED"

I have no idea why it thinks "reg_type" is a possible match.  It seems
very clear that RAM_addr is unsigned, "00" is SLV, and data_in is
SLV.  "&" can only have one possible meaning.  I'm sure that I'm doing
something else wrong that you guys will point out in less than a
second!  ;)

Shannon
[/QUOTE]

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