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VHDL
stumped on syntax yet again!
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[QUOTE="Mike Treseler, post: 3521820"] Make arrays of subtypes, not base types. The problem is inside the parens. "00" is an anonymous type that could be an reg_type *element*. STD_LOGIC_VECTOR(HWID'RANGE) is an anonymous subtype. The LRM does not require the compiler to think further. That's just the way it is. Simplest fix is to declare and use subtypes for the various STD_LOGIC_VECTOR widths. -- Mike Treseler [/QUOTE]
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stumped on syntax yet again!
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