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VHDL
stumped on syntax yet again!
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[QUOTE="Shannon, post: 3521822"] Thanks for the help Mike. I guess I still don't understand. I tried googling for "anonymous subtype" but I didn't find any helpful information. I tried declaring a subtype by doing: subtype hwid_type IS STD_LOGIC_VECTOR(7 DOWNTO 0); and then: TYPE reg_type IS ARRAY (0 TO NUM_REGS-1) OF hwid_type; SIGNAL data_in : hwid_type; That didn't change anything so I'm obviously not understanding the term "anonymous subtype". Any hints? Shannon [/QUOTE]
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stumped on syntax yet again!
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