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VHDL
stumped on syntax yet again!
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[QUOTE="Nicolas Matringe, post: 3521871"] Mike Treseler a écrit : I recently had a similar problem (though I was only using SLVs) and fixed it by pulling the litteral constant out of the cast : RAM_addr <= "00" & unsigned(data_in); In this case the context is clear : "00" must be unsigned to make the assignment valid. I still don't understand why the context is unclear when concatenating a litteral constant and a std_logic_vector. Nicolas [/QUOTE]
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stumped on syntax yet again!
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