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VHDL
stumped on syntax yet again!
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[QUOTE="Shannon, post: 3522399"] You don't have to convince me that it's a bug! hehehe But I always want to understand WHY things are the way they are. The thing I learned here was "scope". I had no idea it was using the concept of scope to resolve ambiguous situations. Personally I think type casting it as an SLV should have worked. Shannon [/QUOTE]
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VHDL
stumped on syntax yet again!
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