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Message: [QUOTE="Rob Dekker, post: 3522466"] Hi Shannon, This is not a bug. As others tried to explain to you, the expression ("00" & data_in) could mean an array of 10 elements of std_logic, or it could mean an array of 2 elements of std_logic_vector. In the first case, the result type is 'std_logic_vector', in the second case it can be type 'reg_type'. The tool cannot know which one you mean because the expression is used as an operand to the type conversion (to type 'UNSIGNED'), and LRM 7.3.5 states explicitly : "The type of the operand of a type conversion must be determinable independent of the context (in particular, independent of the target type)." So either type 'reg_type' or type 'std_logic_vector' could match here. How to fix this ? Work with EITHER 'std_logic_vector' OR with 'unsigned'. Convert between the two as little as you can. That will also make it clear what the representation of the data is in the signals. If you have to convert, do it with a plain conversion (no expression in the argument). So, two solutions : (1) Change 'data_in' to be an 'unsigned'. Then use normal assignment : RAM_addr <= "00" & data_in; (2) If you want to keep 'data_in' the same (type std_logic_vector), then concert it by itself : RAM_addr <= "00" & UNSIGNED(data_in); Either way should work (no ambiguity). Rob [/QUOTE]