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Message: [QUOTE="Shannon, post: 3522702"] Great stuff! Thanks for the detailed explaination. This group is a wonderful resource. I think I followed James's explaination but I have one remaining question. If I (properly) used a subtype to declare my array: subtype hwid_type IS STD_LOGIC_VECTOR(7 DOWNTO 0); TYPE reg_type IS ARRAY (0 TO NUM_REGS-1) OF hwid_type; SIGNAL data_in : hwid_type; Then wouldn't "reg_type" resolve down to SLV and thereby remove the ambiguity? To refer back to James's list we would have: 1a) "&"[std_logic_vector,std_logic_vector RETURN std_logic_vector] 2d) "&"[std_logic_vector,std_logic_vector RETURN reg_type] but reg_type is really a subtype of SLV. So in fact 1a and 2d would be equivalent. (I know I'm wrong. I'm just looking for that last little bit of understanding) Shannon [/QUOTE]