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VHDL
stumped on syntax yet again!
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[QUOTE="James Unterburger, post: 3522805"] Sorry, "reg_type" is not "really a subtype of SLV", it is a subtype of a distinct type (an anonymous array type) whose element subtype is the constrained array subtype "hwid_type". The element *type* is still "std_logic_vector" however, and overloading occurs using only base types, never subtypes. [/QUOTE]
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stumped on syntax yet again!
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