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Message: [QUOTE="Don Ansley, post: 1952903"] KJ, your simple example might be misleading to a novice. The example statement is synthesizable in the context that the synthesis tool 'ignores' the AFTER clause because the tool knows that portion of the statement is not synthesizable at this point in time. This convenience allows designers the ability to add representative delays into the RTL to help with modeling while still allowing the synthesizer to build the logic structures. You are correct in saying that no synthesizer today can synthesize logic to incorporate specific delay characteristics as in the example given. [/QUOTE]