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VHDL
the problem with packages and generics and user defined types(arrays, records, etc)
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[QUOTE="KJ, post: 3436171"] Just what do you mean by 'contradictory type definitions or constants'? Reusing the same type name or constant names in multiple packages? If so, then you can use the 'path name' to the thing in question. Example: Instead of... use pkg_this_package.all; use pkg_that_package.all; ... signal abc : my_type; signal xyz : my_type; you can have (note: no need for 'use' statements) signal abc : work.pkg_this_package.my_type; signal xyz : work.pkg_that_package.my_type; Constants as well can be referred to similarly constant ZZZ: integer := work.pkg_this_package.some_const; Again, I'm not sure if this is the type of issue you're running across or not. You're correct, you can not do this. Sharing between entities is the only reason you would put it in the package to begin with. Any other 'local' constants would be put in the architecture or process body. I don't think there is a solution along the lines of thinking that you're proposing. Kevin Jennings [/QUOTE]
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the problem with packages and generics and user defined types(arrays, records, etc)
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