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Message: [QUOTE="Shannon, post: 4145757"] I struggle with this more than any other subject in VHDL. Ok... from a post by Jonathan Bromley from some time ago: acc <= ('0' & acc(7 downto 0)) + amplitude + acc(8); acc : std_logic_vector(8 downto 0); amplitude : std_logic_vector(7 downto 0); it's such a beautiful line of code to accomplish pwm (DeltaSigma modulator). I would love to keep it as it is without piles of type conversion and casting and what not but alas I don't think that's possible. I've tried all kinds of very unclever combinations of unsigned' this and to_integer that....no glory. Can anyone help? Shannon (struggling with the same issues over and over again) [/QUOTE]