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Message: [QUOTE="Jonathan Bromley, post: 4146277"] sheesh, did I really write that? Out of context? I've been campaigning _against_ the use of std_logic_unsigned for years, and now it turns out I've been virally promoting it all that time :-) The end-around-carry is a very neat trick, yes. I claim no originality. As others have said, it will work just fine if acc and amplitude are both "unsigned", except that you need to make the carry-in be a 1-bit vector. acc(8 downto 8) is the easiest, I think. Other possibilities include unsigned'(0=>acc(8)) ("0" & acc(8)) While we're thinking about alternatives, perhaps parameterizing the vectors would be good: [port] amplitude: in unsigned -- unconstrained ... signal acc: unsigned(amplitude'length downto 0); ... acc <= ('0' & acc(acc'length-2 downto 0)) + amplitude + acc(acc'length downto acc'length); [/QUOTE]