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VHDL
type casting / conversion again
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[QUOTE="Shannon, post: 4146317"] acc <= ('0' & acc(acc'length-2 downto 0)) Ahem....and that looks as beautiful as the original to you? o_O (just teasing). Thank you all for the help. To get through the day I made a separate signal called 'carry' that handled the conversion to an array. I'll go back and retry with the acc(8 downto 8) "trick". This is the reason I ask dumb questions... what do you mean by "std_logic_unsigned"? does this mean I shouldn't be using unsigned? I use it everywhere! Shannon [/QUOTE]
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