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VHDL
type casting / conversion again
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[QUOTE="Tricky, post: 4146568"] Std_logic_unsigned is a non-IEEE package that lets you treat std_logic_vectors as unsigned numbers. It was written by Synopsys about 20 year ago. Unfortunatly, because it was released before the IEEE standard numeric_std, there are many text books and examples that use it, and it becomes a vicious circle as new engineers learn from old text books then recommend the same books to the next generation. Many many experienced engineers use it too. Its in such a situation that in the 2008 standard it got rolled into an IEEE standard. So - dont use it and keep this newsgroup happy :) [/QUOTE]
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