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VHDL
type casting / conversion again
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[QUOTE="Jonathan Bromley, post: 4146583"] Tee hee. No, it's horrid-looking, you're right. But it's less likely to need life-support in the future. Aliases might be your friend here... alias acc_MSB_value: unsigned (0 downto 0) is acc(acc'left downto acc'left); alias acc_without_MSB: unsigned(acc'length-2 downto 0) is acc(acc'length-2 downto 0); .... acc <= ('0' & acc_without_MSB) + amplitude + acc_MSB_value; Beauty restored :-) [/QUOTE]
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