Reply to thread

Message

[QUOTE="Jonathan Bromley, post: 4146617"]
Yes - good catch.  Sorry.

Yes, the MSB is always 'left and I probably should have
used that.  However, there's still another potential
goof because when writing
   acc(acc'left downto acc'left)
you need to choose "to" or "downto" based on the original
declaration of acc.  However, if you get that wrong the compiler
will pick it up.

I wish it were possible to declare unconstrained arrays
in VHDL with the to/downto direction constrained:

type jonathans_unsigned is array(natural range >) of ...

(where "range <>" allows both to/downto, "range >" allows
only downto, "range <" allows only to) so that it would
then be illegal to declare any jonathans_unsigned with
a "to" direction.  But it is not so :-(

The standard defence against being given an array that
might have inappropriate direction is to copy or alias
it onto an array whose subscript range you've normalized.
I'm pretty paranoid about always doing that in real code,
but I got sloppy in this morning's post.

Thanks

Jonathan
[/QUOTE]

Verification