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VHDL
type computation
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[QUOTE="KJ, post: 4114111"] You need functions to compute the sfixed array bounds. What you've shown is declaring a signal that is of a type computed by a function...which is illegal. Once you get your two functions, the signal declarations will be something like this... signal coeff_a0 : sfixed(fixdt_to_sfixed_left(COEFFICIENT_WORDLENGTH, COEFFICIENT_FRACTIONLENGTH) downto fixdt_to_sfixed_right(COEFFICIENT_WORDLENGTH, COEFFICIENT_FRACTIONLENGTH)); KJ [/QUOTE]
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