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Message: [QUOTE="Tricky, post: 4114141"] I am currently in the process of getting simulink algorithms working in VHDL, and doing a lot of co-simulation. I think the approach you have may be the wrong way round. When we started, we looked at the limitations the FPGA was going to impose on the algorithm, rather than letting simulink run the show completly. Things like multiplier widths (normally 18 bits) and available memory at given points. This all fed back and put fixed limits on the word widths at the start (after some testing was done on the algorithm to ensure it didnt degrade performance). So I have a "setup package" that defines all of the word widths throughout the algorithm via sub types. I have the following: subtype filter_word_t is sfixed(11 downto -4); --16 bits because the memories are 18 bits and we need to store a couple of status bits with each word subtype coeff_t is sfixed(1 downto -16); --18 bit multiplers. then you can start doing all the stuff VHDL is good for: type coeff_array_t is array(-1 to 1, -1 to 1) of coeff_t; type filter_array_t is array(natural range <>) of coeff_array_t; -- Will co-simulation support 3+D arrays any time soon? The good thing about this is, if we really need to change the widths, all I need to do is change the setup package manually and the whole thing still works - make sure you use the 'length/'high/'low attributes all over the place. Whether it will still fit, and whether the algorithm guys will understand this is another question! [/QUOTE]

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