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Message: [QUOTE="Weng Tianxiang, post: 2732756"] Hi KJ, 1. Q <= (C and D) or (not(C) and Q); I have never seen such equation in my coding experiences and have no idea how this equation would be written. The logic result is beyond a reason. Could you please write it in equivalent latch equation in informal VHDL? 2. FPGA of Xilinx chip really has latch primative and one may use it using latch primative to call it. But it is hard to refer to it in VHDL. I don't mean VHDL should have included latch statement, what I mean is VHDL really lacks the statement element to refer to a latch in a clear and reliable way and the lack can be easily corrected. Thank you. Weng [/QUOTE]