8bit * 8bit pipelined multiplier

Discussion in 'VHDL' started by humble, Oct 28, 2006.

  1. humble

    humble

    Joined:
    Oct 28, 2006
    Messages:
    1
    Hello good-day,

    I am in real need of some help. Right now i'm at college programming using Verilog.
    I need some assistance in programming using Verilog, an 8bit * 8bit pipelined multiplier. In the design, I am required to use an array of CSA (carry save adders) and one CPA to find the final product.

    Can I have some urgent help pleaseeeeeeee, I really need it!

    Thank you!

    Regards,

    Humble
     
    humble, Oct 28, 2006
    #1
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