Generic N-bit multiplier

Discussion in 'VHDL' started by hachidan, Sep 23, 2011.

  1. hachidan

    hachidan

    Joined:
    Sep 23, 2011
    Messages:
    2
    Hi, my name is An Nguyen and I cannot figure out how set up my n-bit multiplier correctly. I am fairly confident in my logic sequential statements but as far as unsigned vs (std_logic_vector)slv is concerned I need clarification. I have written a test program to see how i can fix my n-bit multiplier but i am at a lost. Some comments are are the end of the test code that states some of my specific problems.

    ----------n - bit multiplier--------

    Library IEEE;

    Use ieee.std_logic_1164.all;
    Use ieee.std_logic_arith.all;
    Use ieee.std_logic_unsigned.all;

    Entity multBehv is
    Generic(N : integer := 4);
    Port(a, b : in std_logic_vector((N-1) downto 0);
    s : out std_logic_vector(((2*N) - 1) downto 0));
    End entity;

    Architecture multBehv_arch of multBehv is

    Signal accSig : std_logic_vector(((2*N) - 1) downto 0) := (others => '0'); -- accumulator signal
    Constant zeroC : std_logic_vector((N - 1) downto 0) := (others => '0'); -- zero concatination signal
    Signal iSig : std_logic_vector(((2*N) - 1) downto 0) := (others => '0');

    Begin

    mult : process (a, b) is
    Variable i : integer := N;
    Begin
    While (i > 0) loop -- allows n bit multiplication larger than 4 bits
    if (b(N-i) = '1') then
    if (i = N) then
    iSig <= (zeroC((i-1) downto 0) & a);
    accSig <= accSig + iSig;
    i := i - 1;
    elsif (i = (N-1)) then
    iSig <= (zeroC((i-1) downto 0) & (a & zeroC(0)));
    accSig <= accSig + iSig;
    i := i - 1;
    elsif ((i < (N-1)) and (i > 1)) then
    iSig <= (zeroC((i-1) downto 0) & (a & zeroC(((N-i)-1) downto 0)));
    accSig <= accSig + iSig;
    i := i - 1;
    elsif (i = 1) then
    iSig <= (zeroC(0) & (a & zeroC(((N-i)-1) downto 0)));
    accSig <= accSig + iSig;
    i := i - 1;
    end if;
    else
    accSig <= accSig;
    i := i - 1;
    end if;
    end loop;

    s <= accSig;
    i := N;

    End process;

    End architecture;
    ---------------------------------------------

    ----------testing code-----

    library IEEE;

    use ieee.std_logic_1164.all;
    use ieee.std_logic_arith.all;
    use ieee.std_logic_unsigned.all;

    Entity a is
    port(i : in std_logic_vector(7 downto 0); o : out std_logic_vector(15 downto 0));
    End entity;

    Architecture aa of a is
    Signal a, b, x, z : unsigned(15 downto 0);
    Signal c,d,e, f, g : unsigned(7 downto 0);
    begin

    c <= "01010100";
    d <= "00000000";
    e <= "11111111";
    f <= "11110000";

    a <= "0000000000000011";

    a <= a + (c(3 downto 0) & d (3 downto 0) & e);

    --if i have like x <= (c(3 downto 0) & d (3 downto 0) & e);
    -- b <= a + x it comes out to the correct answer
    -- but as soon as i try to accumulate a, like above, the output is all x es
    -- i am using modelsim, and i stepped through these different scenarios but the ordering in -- which signal obtained the desired valued was very confusing

    o <= std_logic_vector(a);

    end architecture;
    ----------------
    hachidan, Sep 23, 2011
    #1
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  2. hachidan

    hachidan

    Joined:
    Sep 23, 2011
    Messages:
    2
    I figured it out. Basically i was right and I just needed to use variables to do the multiplication logic then store it to the output after the loop, using slv.
    hachidan, Sep 30, 2011
    #2
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