Hi
I want to write a simple demux, yet I wanted to make it as short as possible. Therefore I used conv_integer, but it showed me a strange error (I'm using quartus 6.0, and have tried the same program in ISE). The error makes somewhat sense, but I want to find a solution so that I don't have to use case (and be able to use a generic).
Here is the code:
Library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
Entity Demux is
port (I : in std_logic;
S: in std_logic_vector(2 downto 0);
Q: out std_logic_vector(7 downto 0));
End entity;
Architecture behave of Demux is
Begin
Process(S,I)
Begin
Q <= (conv_integer(unsigned(s)) => I, others => 'Z');
end process;
end architecture;
The error that shows up is:
Error (10318 ): VHDL aggregate error at demux.vhd(16): choice must be constant
Thank you for your help.
I want to write a simple demux, yet I wanted to make it as short as possible. Therefore I used conv_integer, but it showed me a strange error (I'm using quartus 6.0, and have tried the same program in ISE). The error makes somewhat sense, but I want to find a solution so that I don't have to use case (and be able to use a generic).
Here is the code:
Library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
Entity Demux is
port (I : in std_logic;
S: in std_logic_vector(2 downto 0);
Q: out std_logic_vector(7 downto 0));
End entity;
Architecture behave of Demux is
Begin
Process(S,I)
Begin
Q <= (conv_integer(unsigned(s)) => I, others => 'Z');
end process;
end architecture;
The error that shows up is:
Error (10318 ): VHDL aggregate error at demux.vhd(16): choice must be constant
Thank you for your help.