A Question About Concatenation in VHDL

Discussion in 'VHDL' started by Karsus, Nov 22, 2011.

  1. Karsus

    Karsus

    Joined:
    Nov 22, 2011
    Messages:
    2
    Hello Everyone, I'm very new to VHDL and to this forum so If my question doesn't belong here or already answered I apologize, here's my question, when we concatenate bits to a vector will it be any faster than a for loop to do it?
    Here's an example, imagine we have a sign extension in our system(let say 4 bit to 8 bit)
    which of the following code would be faster and safer to use?

    Code:
    bit8(3 downto 0)<=bit4(3 downto 0);
    
    bit8(7 downto 4)<=bit4(3)&bit4(3)&bit4(3)&bit4(3);
    
    
    OR,

    Code:
    bit8(3 downto 0)<=bit4(3 downto 0);
    
    for i in 7 downto 4 loop
    	bit8(i)<=bit4(3);
    end loop;
    
    Thank you for your help,
    Karsus, Nov 22, 2011
    #1
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  2. Karsus

    jeppe

    Joined:
    Mar 10, 2008
    Messages:
    348
    Location:
    Denmark
    Hi

    Please remember - VHDL a Hardware Description Language.

    Hence will the result of your code (if not it's for simulation) be a circuit of logic devices
    (Properly inside a FPGA)

    If both your solutions gives the wanted hardware and functionality (and I beleive it does)
    then you shouldn't care.

    But I agree that your computer could use, say 0.00001 seconds Synthesizing the code.

    Your welcome
    jeppe, Nov 22, 2011
    #2
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  3. Karsus

    Karsus

    Joined:
    Nov 22, 2011
    Messages:
    2
    Hi Jeppe,
    Thank you for your answer, I think I should stop treating vhdl as a High level programming language...
    Karsus, Nov 22, 2011
    #3
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