a small clarification please

Discussion in 'VHDL' started by naren, Aug 19, 2009.

  1. naren

    naren Guest

    hello friends good morning. I am using Xilinxs Spartan 3 board which
    developed by ADM company. I am using webpack ISE 9.1i, in that i
    wrote a code for seven segment display.
    The code looks like this

    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
    use IEEE.STD_LOGIC_ARITH.ALL;
    use IEEE.STD_LOGIC_UNSIGNED.ALL;

    entity ssg3 is
    Port ( bcd : in STD_LOGIC_VECTOR (3 downto 0);
    seg1 : out STD_LOGIC_VECTOR (7 downto 0);
    x : out STD_LOGIC_VECTOR (3 downto 0));
    end ssg3;

    architecture Behavioral of ssg3 is

    begin
    process(bcd)

    begin
    x<= "1110";


    case bcd is
    when "0000" => seg1 <= "11111100";
    when "0001" => seg1 <= "01100000";
    when "0010" => seg1 <= "11011010";
    when "0011" => seg1 <= "11110010";

    when "0100" => seg1 <= "01100110";
    when "0101" => seg1 <= "10110110";
    when "0110" => seg1 <= "10111110";
    when "0111" => seg1 <= "11100000";
    when "1000" => seg1 <= "11111110";
    when "1001" => seg1 <= "11110110";
    when "1010" => seg1 <= "11101110";
    when "1011" => seg1 <= "00111110";
    when "1100" => seg1 <= "10011100";
    when "1101" => seg1 <= "01111010";
    when "1110" => seg1 <= "10011110";
    when "1111" => seg1 <= "10001110";
    when others => seg1 <= "--------";

    end case;
    end process;
    end Behavioral;

    here 'x' is for selecting segment only, because i have four segments
    in my kit.
    If i implement this code on the FPGA i am getting display when ever i
    give bcd inputs externally. I am not getting continuous display. I
    tried to put loop for continuous display, but i am not succeeded. Can
    you please tell me the procedure to continous display on sevensegment
    from "0 to F".

    I also tried in the following way but i didn't get continuous
    display.

    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
    use IEEE.STD_LOGIC_ARITH.ALL;
    use IEEE.STD_LOGIC_UNSIGNED.ALL;

    entity ssg4 is
    Port ( clk : in std_logic;
    seg1 : out STD_LOGIC_VECTOR (7 downto 0);
    x : out STD_LOGIC_VECTOR (3 downto 0));
    end ssg4;

    architecture Behavioral of ssg4 is



    signal bcd : std_logic_vector( 3 downto 0);


    begin
    process(clk,bcd)

    begin
    if clk'event and clk ='1' then
    bcd <= bcd+1;
    x <= "1110";

    case bcd is
    when "0000" => seg1 <= "11111100";
    when "0001" => seg1 <= "01100000";
    when "0010" => seg1 <= "11011010";
    when "0011" => seg1 <= "11110010";
    when "0100" =>
    seg1 <= "01100110";
    when "0101" => seg1 <= "10110110";
    when "0110" => seg1 <= "10111110";
    when "0111" => seg1 <= "11100000";
    when "1000" => seg1 <= "11111110";
    when "1001" => seg1 <= "11110110";
    when "1010" => seg1 <= "11101110";
    when "1011" => seg1 <= "00111110";
    when "1100" =>
    seg1 <= "10011100";
    when "1101" => seg1 <= "01111010";
    when "1110" => seg1 <= "10011110";
    when "1111" => seg1 <= "10001110";
    when others => seg1 <= "--------";
    end case;
    end if;
    end process;
    end Behavioral;


    Please give me the way i can produce the continuous display on seven
    segment.
    I am waiting for your response.
    naren, Aug 19, 2009
    #1
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  2. naren

    JimLewis Guest

    Have you tried just displaying a single constant value in one element
    of the displays. After you learn that, then you are ready for more.
    There is lots of misunderstandings that could make the problem not
    work. Try small experiments and build up to what you need it to do.

    Good luck,
    Jim
    JimLewis, Aug 21, 2009
    #2
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  3. naren

    debayan_p

    Joined:
    Jun 2, 2009
    Messages:
    23
    "Please give me the way i can produce the continuous display on seven
    segment."

    -----------------------------------------

    U may be messing up with the refresh rate of the displays.


    Check that out !!
    debayan_p, Aug 24, 2009
    #3
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