Accessing field of record aggregate

Discussion in 'VHDL' started by Mark Christiaens, May 11, 2011.

  1. I was wondering what is going on in this test case:
    ---------------------------------------------
    entity top is
    end entity top;

    architecture RTL of top is
    type rtype is record
    i1 : integer;
    i2 : integer;
    end record;

    begin
    process is
    variable i : rtype;
    begin
    i := rtype'(0, 0); -- OK
    assert i.i1 = 0; -- OK
    assert rtype'(0, 0).i1 = 0; -- Not OK
    wait;
    end process;

    end architecture RTL;
    ---------------------------------------------

    As you can see, I've defined a record type "rtype". Using a record
    aggregate to initialize a record variable is fine (according to
    ModelSim ALTERA STARTER EDITION 6.5e), accessing the "i1" field of
    that variable is fine but building a complete expression that uses the
    record aggregate is not fine. ModelSim complains:

    # -- Loading package standard
    # -- Compiling entity top
    # -- Compiling architecture rtl of top
    # ** Error: top.vhd(18): Qualified expression type mark rtype is not
    type std.standard.boolean.
    # ** Error: top.vhd(18): near ".": expecting ';'
    # ** Error: top.vhd(22): VHDL Compiler exiting

    Why exactly is this not allowed?
    ---
    Mark Christiaens
    Discover the Future of VHDL Design
    www.sigasi.com
    Mark Christiaens, May 11, 2011
    #1
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  2. Mark Christiaens wrote:

    > I was wondering what is going on in this test case:
    > ---------------------------------------------
    > entity top is
    > end entity top;
    >
    > architecture RTL of top is
    > type rtype is record
    > i1 : integer;
    > i2 : integer;
    > end record;
    >
    > begin
    > process is
    > variable i : rtype;
    > begin
    > i := rtype'(0, 0); -- OK


    There is no ambiguity, so a qualifier is not needed. This works just as
    well:
    i := (0, 0);

    Or:
    i := (i1 => 0, i2 => 0);

    Even this is OK:

    i := (others => 0);

    > assert i.i1 = 0; -- OK
    > assert rtype'(0, 0).i1 = 0; -- Not OK
    > wait;
    > end process;
    >
    > end architecture RTL;
    > ---------------------------------------------
    >
    > As you can see, I've defined a record type "rtype". Using a record
    > aggregate to initialize a record variable is fine (according to
    > ModelSim ALTERA STARTER EDITION 6.5e), accessing the "i1" field of
    > that variable is fine but building a complete expression that uses the
    > record aggregate is not fine. ModelSim complains:
    >
    > # -- Loading package standard
    > # -- Compiling entity top
    > # -- Compiling architecture rtl of top
    > # ** Error: top.vhd(18): Qualified expression type mark rtype is not
    > type std.standard.boolean.
    > # ** Error: top.vhd(18): near ".": expecting ';'
    > # ** Error: top.vhd(22): VHDL Compiler exiting
    >
    > Why exactly is this not allowed?


    I don't know exactly why. But I also don't know why you would want to use
    that construct that way. Taking a record element works with variables,
    constants and signals.

    It seems that you want to use a constant built with literals. Using a real
    constant avoids the whole problem

    constant c : rtype := (0, 0);
    ...
    assert c.i1 = 0; -- OK

    --
    Paul Uiterlinden
    www.aimvalley.nl
    e-mail addres: remove the not.
    Paul Uiterlinden, May 11, 2011
    #2
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  3. On May 12, 12:29 am, Alan Fitch <> wrote:
    > On 11/05/11 10:46, Mark Christiaens wrote:
    >
    >
    >
    >
    >
    >
    >
    >
    >
    > > I was wondering what is going on in this test case:
    > > ---------------------------------------------
    > > entity top is
    > > end entity top;

    >
    > > architecture RTL of top is
    > >     type rtype is record
    > >         i1 : integer;
    > >         i2 : integer;
    > >     end record;

    >
    > > begin
    > >     process is
    > >         variable i : rtype;
    > >     begin
    > >         i := rtype'(0, 0); -- OK
    > >         assert i.i1 = 0; -- OK
    > >         assert rtype'(0, 0).i1 = 0; -- Not OK
    > >         wait;
    > >     end process;

    >
    > > end architecture RTL;
    > > ---------------------------------------------

    >
    > > As you can see, I've defined a record type "rtype".  Using a record
    > > aggregate to initialize a record variable is fine (according to
    > > ModelSim ALTERA STARTER EDITION 6.5e), accessing the "i1" field of
    > > that variable is fine but building a complete expression that uses the
    > > record aggregate is not fine.  ModelSim complains:

    >
    > > # -- Loading package standard
    > > # -- Compiling entity top
    > > # -- Compiling architecture rtl of top
    > > # ** Error: top.vhd(18): Qualified expression type mark rtype is not
    > > type std.standard.boolean.
    > > # ** Error: top.vhd(18): near ".": expecting ';'
    > > # ** Error: top.vhd(22): VHDL Compiler exiting

    >
    > > Why exactly is this not allowed?

    >
    > In section 6.1 the VHDL standard defines a name as
    >
    >   simple_name | operator_symbol | selected_name | indexed_name |
    > slice_name | attribute_name
    >
    > It then defines the prefix of a selected name as
    >
    >   prefix ::= name | funtion_call
    >
    > A qualified expression is not a name so the selected_name you've
    > attempted to use is also not a name.
    >
    > It doesn't seem surprising to me as you haven't created an object with a
    > name, just a literal.
    >
    > regards
    > Alan
    >
    > P.S. Cadence ncvhdl helpfully says
    >
    >  assert rtype'(0,0).i1 = 0;
    >                       |
    > ncvhdl_p: *E,QLXNOP (test.vhd,18|22): a qualified expression is not a
    > legal name prefix [6.1] [7.3.4].
    >         errors: 1, warnings: 0
    > irun: *E,VHLERR: Error during parsing VHDL file (status 1), exiting.
    >
    > --
    > Alan Fitch


    I was not having a particular use case in mind. I was just curious
    how "orthogonal" the VHDL grammar exactly is with regards to such
    expressions. My conclusion is that it's not very orthogonal ;)

    Anyway, thank you for clarifying.

    Mark
    Mark Christiaens, May 12, 2011
    #3
  4. Mark Christiaens

    KJ Guest

    On May 12, 4:00 am, Mark Christiaens <>
    wrote:
    > I was just curious
    > how "orthogonal" the VHDL grammar exactly is with regards to such
    > expressions.  My conclusion is that it's not very orthogonal ;)
    >


    My conclusion is that your usage is not a measure of orthogonality.

    KJ
    KJ, May 12, 2011
    #4
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