Adding internal signals in Modelsim

[ALuPin]

Dear Sir or Madam,

I have a question concerning Modelsim:

In a VHDL testbench I instantiate the module "packetfile_ctrl.vhd"
as U1

In the attached macro I add waves. These waves are inputs and outputs
of the module "packetfile_ctrl.vhd".
But what if I want to view internal signals? For example the internal
signal
last_block:
If I write the following command in my macro I do not get a wave of
this signal
"add wave sim:/tb_packetfile_ctrl/u1/last_block"
So how can I add an internal signal?
Is there an alternative way without using the macro (this means
adding a wave belatedly when the waveform - editor is already opened)
?

Thank you for your help.

Best regards
Andrés Vázquez
G&D

MACRO:
cd H:/EDA/Altera/Extender/Packetfile_Ctrl/simulation/modelsim
vlib modelsim_work
vmap work modelsim_work
vsim -sdftyp /U1=packetfile_ctrl_vhd.sdo work.TB_PACKETFILE_CTRL
vcom -93 -reportprogress 300 -work work
{H:/EDA/Altera/Extender/Packetfile_Ctrl/simulation/modelsim/PACKETFILE_CTRL.vho}
vcom -93 -reportprogress 300 -work work
{H:/EDA/Altera/Extender/Packetfile_Ctrl/simulation/modelsim/TB_PACKETFILE_CTRL.vhd}
view signals
view wave
vsim work.TB_PACKETFILE_CTRL
add wave sim:/tb_packetfile_ctrl/u1/P_clk_in
add wave sim:/tb_packetfile_ctrl/u1/P_clk_out
add wave sim:/tb_packetfile_ctrl/u1/Reset
add wave sim:/tb_packetfile_ctrl/u1/Write
add wave sim:/tb_packetfile_ctrl/u1/Read
add wave sim:/tb_packetfile_ctrl/u1/last_block ?????????????????

 

[ALuPin]

Some additional question:
Is the shown macro for functinal or for timing simulation ?
The background of this question: When I run the simulation and
open the "signals" window --> ADD WAVE ---> ALL SIGNALS IN DESIGN
I can find the original names of the primary inputs and outputs
but I can NOT find the original internal names, these seem to be
renamed by the compiler.
If I want to analyse a state machine it is impossible without
the original names.

So my question: How can I simulate (functional) without losing
the original names ?

 

[Mike Treseler]

If I write the following command in my macro I do not get a wave of
this signal
"add wave sim:/tb_packetfile_ctrl/u1/last_block"

try:

add wave sim:/tb_packetfile_ctrl/u1/*

or from the gui:

view,structure,right-click on u1, add, add to wave

If that doesn't do it, the signal is not there.

MACRO:
cd H:/EDA/Altera/Extender/Packetfile_Ctrl/simulation/modelsim
vlib modelsim_work
vmap work modelsim_work
vsim -sdftyp /U1=packetfile_ctrl_vhd.sdo work.TB_PACKETFILE_CTRL

Wait a minute. You are siming a netlist, not source code.
This may be the reason last_block is gone.
Compile the source files and try
vsim TB_PACKETFILE_CTRL

-- Mike Treseler

 

[ALuPin]

try:

add wave sim:/tb_packetfile_ctrl/u1/*

or from the gui:

view,structure,right-click on u1, add, add to wave

If that doesn't do it, the signal is not there.


Wait a minute. You are siming a netlist, not source code.
This may be the reason last_block is gone.
Compile the source files and try
vsim TB_PACKETFILE_CTRL

Hi,

what do you mean with "Compile the source files" ?
Compiling the source files in Modelsim or in QuartusII (Processing
->Start Compilation) ?
When I compile the design in QuartusII and use the following (changed)
macro
I cannot find the internal names yet. (like for example last_block).
last_block is visible somehow, but only in combination with different
additional
signals like dataa, datab, datac, datad, aclr, aload, sclr, sload ...

MACRO
cd H:/EDA/Altera/USB_Extender/Packetfile_Ctrl/simulation/modelsim
vlib modelsim_work
vmap work modelsim_work
vsim TB_PACKETFILE_CTRL
vcom -93 -reportprogress 300 -work work
{H:/EDA/Altera/USB_Extender/Packetfile_Ctrl/simulation/modelsim/PACKETFILE_CTRL.vho}
vcom -93 -reportprogress 300 -work work
{H:/EDA/Altera/USB_Extender/Packetfile_Ctrl/simulation/modelsim/TB_PACKETFILE_CTRL.vhd}
view signals
view wave
vsim work.TB_PACKETFILE_CTRL
add wave sim:/tb_packetfile_ctrl/u1/P_clk_in
add wave sim:/tb_packetfile_ctrl/u1/P_clk_out
add wave sim:/tb_packetfile_ctrl/u1/Reset
add wave sim:/tb_packetfile_ctrl/u1/Write
add wave sim:/tb_packetfile_ctrl/u1/Read
add wave sim:/tb_packetfile_ctrl/u1/Data_in
add wave sim:/tb_packetfile_ctrl/u1/Addr_in
add wave sim:/tb_packetfile_ctrl/u1/In_Last_byte
add wave sim:/tb_packetfile_ctrl/u1/Initial_f
add wave sim:/tb_packetfile_ctrl/u1/Data_out
add wave sim:/tb_packetfile_ctrl/u1/Addr_out
run 15000ns

- Andres Vazquez

 

[fe]

vcom -93 -reportprogress 300 -work work{H:/EDA/Altera/Extender/Packetfile_Ctrl/simulation/modelsim/PACKETFILE_CTRL.
vho}

You must compile in modelsim your rtl file (vhdl source) packetfile_ctrl.vhd
and not the gate file (netlist) packetfile_ctrl.vho produce by quartus after
synthesis.

vcom -93 -reportprogress 300 -work work packetfile_ctrl.vhd

regards
fe

 

[ALuPin]

{H:/EDA/Altera/Extender/Packetfile_Ctrl/simulation/modelsim/PACKETFILE_CTRL.
vho}

You must compile in modelsim your rtl file (vhdl source) packetfile_ctrl.vhd
and not the gate file (netlist) packetfile_ctrl.vho produce by quartus after
synthesis.

vcom -93 -reportprogress 300 -work work packetfile_ctrl.vhd

regards
fe

Hi,

thank you for your answer:

The MACRO now looks like that but I still get the following error
message:

"Cannot find QuartusIIVersion3.0(D:/Programme/win32aloem/...altera/Vhdl/src/
altera_mf/altera_mf.vhd)
Source unavailable"

Where could be the problem?
What does "altera_mf.vhd" include?


cd H:/EDA/Altera/Extender/Packetfile_Ctrl/simulation/modelsim
vlib modelsim_work
vmap work modelsim_work
vsim TB_PACKETFILE_CTRL
vcom -93 -reportprogress 300 -work work
{H:/EDA/Altera/Extender/Packetfile_Ctrl/PACKETFILE_CTRL.vhd}
vcom -93 -reportprogress 300 -work work
{H:/EDA/Altera/Extender/Packetfile_Ctrl/simulation/modelsim/TB_PACKETFILE_CTRL.vhd}
view signals
view wave
vsim work.TB_PACKETFILE_CTRL
add wave sim:/tb_packetfile_ctrl/u1/P_clk_in
add wave sim:/tb_packetfile_ctrl/u1/P_clk_out
add wave sim:/tb_packetfile_ctrl/u1/Reset
add wave sim:/tb_packetfile_ctrl/u1/Write
add wave sim:/tb_packetfile_ctrl/u1/Read
run 15000ns


Best regards
Andrés