All are unsigned but wrong type is output?

[laserbeak43]

Hello,

I was wondering if anyone could help. I've included the code for 4
files of my project. If anyone has the Altera DE2, It's from Lab6 Part
1.

My problem is that in full8bitadder.vhd, i'm getting an error that
says:
Error (10381): VHDL Type Mismatch error at full8bitadder.vhd(17):
indexed name returns a value whose type does not match "UNSIGNED", the
type of the target expression

this error occurs on the line where fa0 is instantiated. I don't
understand why the type would not match unsigned when EVERYTHING in my
project is unsigned.

Does anyone here have an idea of what's happening?

Thanks,
Malik

------------------------------------------------- Lab1_6.vhd
----------------------------------------------------------------

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;

entity Lab1_6 is
port(
SW : in unsigned(15 downto 0);
KEY : in unsigned(1 downto 0);
LEDR : out unsigned(7 downto 0);
LEDG : out unsigned(8 downto 8);
HEX7, HEX6,
HEX5, HEX4,
HEX1, HEX0 : out unsigned(6 downto 0)
);
end Lab1_6;

architecture behavior of Lab1_6 is
signal ci0 : unsigned;
signal S : unsigned(7 downto 0);
signal R : unsigned(7 downto 0);
begin

ci0 <= to_unsigned(1,1);
fa : work.full8bitadder port map(ci0, SW(15 downto 8), SW(7 downto
0), LEDG, R);

h7 : work.HEX port map(SW(15 downto 12), HEX7);
h6 : work.HEX port map(SW(11 downto 8), HEX6);
h5 : work.HEX port map(SW(7 downto 4), HEX5);
h4 : work.HEX port map(SW(3 downto 0), HEX4);
h1 : work.HEX port map(S(7 downto 4), HEX1);
h0 : work.HEX port map(S(3 downto 0), HEX0);

process(KEY)
begin
if(KEY = "01") then
S <= to_unsigned(0,8);
end if;
if(KEY = "10") then
S <= R;
end if;
end process;

end behavior;

------------------------------------------------- full8bitadder.vhd
----------------------------------------------------------------

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;

entity full8bitadder is
port(
ci : in unsigned(7 downto 0);
a, b : in unsigned(7 downto 0);
co : out unsigned(8 downto 0);
s : out unsigned(7 downto 0)
);
end full8bitadder;

architecture behavior of full8bitadder is
begin

fa0 : work.fulladder port map(ci(0), a(0), b(0), co(1), s(0));
fa1 : work.fulladder port map(ci(1), a(1), b(1), co(2), s(1));
fa2 : work.fulladder port map(ci(2), a(2), b(2), co(3), s(2));
fa3 : work.fulladder port map(ci(3), a(3), b(3), co(4), s(3));
fa4 : work.fulladder port map(ci(4), a(4), b(4), co(5), s(4));
fa5 : work.fulladder port map(ci(5), a(5), b(5), co(6), s(5));
fa6 : work.fulladder port map(ci(6), a(6), b(6), co(7), s(6));
fa7 : work.fulladder port map(ci(7), a(7), b(7), co(8), s(7));

end behavior;

------------------------------------------------- fulladder.vhd
----------------------------------------------------------------

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;

entity fulladder is
port(
ci, a, b : in unsigned;
co, s : out unsigned
);
end fulladder;

architecture behavior of fulladder is
begin
s <= a xor b xor ci;
co <= (a and b) or (b and ci) or (a and ci);
end behavior;

------------------------------------------------- HEX.vhd
----------------------------------------------------------------

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;

entity HEX is
port( HEXcnt : in unsigned(3 downto 0);
HEXOut : out unsigned(6 downto 0)
);
end HEX;

architecture behavioral of HEX is

signal HEXInt : integer;

type SegROM is array (0 to 15) of unsigned(6 downto 0);
constant segStates : SegROM := (
0 => "1000000",
1 => "1111001",
2 => "0100100",
3 => "0110000",
4 => "0011001",
5 => "0010010",
6 => "0000010",
7 => "1111000",
8 => "0000000",
9 => "0010000",
10 => "0001000",
11 => "0000011",
12 => "1000110",
13 => "0100001",
14 => "0000110",
15 => "0001110");

begin

process(HEXcnt, HEXInt) begin

HEXInt <= to_integer(unsigned(HEXcnt));
HEXOut <= segStates(HEXInt);

end process;

end behavioral;

 

[Pieter Hulshoff]

this error occurs on the line where fa0 is instantiated. I don't

understand why the type would not match unsigned when EVERYTHING in my
project is unsigned.

entity fulladder is
port(
ci, a, b : in unsigned;
co, s : out unsigned
);
end fulladder;

Try using std_logic here in stead of unsigned vectors of undetermined length.

Kind regards,

Pieter Hulshoff

 

[Thomas Stanka]

I was wondering if anyone could help. I've included the code for 4
files of my project. If anyone has the Altera DE2, It's from Lab6 Part
1. [..]
        fa0 : work.fulladder port map(ci(0), a(0), b(0), co(1), s(0)); [..]
entity fulladder is
                ci, a, b        : in unsigned;
                co, s           : out unsigned

I think the problem is, that numeric_std defines unsigned as array of
std_logic which means the single element is std_logic not unsigned. If
you change the type of these 5 IOs to std_logic, everything should
work.

bye Thomas

 

[laserbeak43]

Hi guys,
Thanks for the replies, that did work, I have to remember that
unsigned is an array of std_logic.
very tricky stuff!

Thanks,
Malik