Arbitrary Clock Frequencies From Base Clock

Discussion in 'VHDL' started by abhisheknag@gmail.com, Jun 19, 2006.

  1. Guest

    Hello,

    I have a board with the Xilinx V2 Pro (xc2vp30). I am designing a BPSK
    demodulator on this board. For the demodulator, I need to generate
    arbitrary clock frequencies from 8 MHz to 10 MHz in 100 kHz increments
    from the base clock. How can I do this? Does anyone have any VHDL code
    I can use for this?

    Thanks and regards,

    Abhishek
    , Jun 19, 2006
    #1
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  2. Guest

    Hi,

    I do this using this simple Numeric Controlled Oscillator -NCO- code I
    found in here: http://www.analogservices.com/vhdlmod.htm
    However the generated clk is not pure in the sense that some periods
    are a bit longer than others.

    Robert

    ha escrit:
    > Hello,
    >
    > I have a board with the Xilinx V2 Pro (xc2vp30). I am designing a BPSK
    > demodulator on this board. For the demodulator, I need to generate
    > arbitrary clock frequencies from 8 MHz to 10 MHz in 100 kHz increments
    > from the base clock. How can I do this? Does anyone have any VHDL code
    > I can use for this?
    >
    > Thanks and regards,
    >
    > Abhishek
    , Jun 19, 2006
    #2
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  3. Rtafas Guest

    What is your master clock? If it is n*100khz, you may use a counter,
    the simplest way is count until you reach the "divider number -1" and
    generate an enable pulse. You will not get a 50% duty cycle clock (but
    you can count to generate it twice higher than you need and divide by
    two). The jitter will be the one from your oscilator.

    A DCO (or NCO) is good too, but only if jitter is not a problem (it is
    said that jitter is a master clock cycle plus the oscillator, but I
    have never found such calculations).

    Also, you may need to lock this clock, so, locked loop is the way (PLL,
    DPLL or ADPLL).

    Also, a good reading about counters and digital synchronous design are
    a very good starting points to understand the codes you may found
    (IMHO, it is fundamental). Google for it!

    Regards,

    Rtafas

    wrote:
    > Hello,
    >
    > I have a board with the Xilinx V2 Pro (xc2vp30). I am designing a BPSK
    > demodulator on this board. For the demodulator, I need to generate
    > arbitrary clock frequencies from 8 MHz to 10 MHz in 100 kHz increments
    > from the base clock. How can I do this? Does anyone have any VHDL code
    > I can use for this?
    >
    > Thanks and regards,
    >
    > Abhishek
    Rtafas, Jun 19, 2006
    #3
  4. Following on from Rtafas,
    if your master clock is n*50khz then
    you should be able to achieve a 50:50 duty cycle clock by loading a count
    and a half count value then when counting if your below the half count out =
    '1' and when above half count out = '0' this should achieve a near 50:50
    duty cycle clock.

    Hope this is of help.

    REGARDS IAN.

    "Rtafas" <> wrote in message
    news:...
    > What is your master clock? If it is n*100khz, you may use a counter,
    > the simplest way is count until you reach the "divider number -1" and
    > generate an enable pulse. You will not get a 50% duty cycle clock (but
    > you can count to generate it twice higher than you need and divide by
    > two). The jitter will be the one from your oscilator.
    >
    > A DCO (or NCO) is good too, but only if jitter is not a problem (it is
    > said that jitter is a master clock cycle plus the oscillator, but I
    > have never found such calculations).
    >
    > Also, you may need to lock this clock, so, locked loop is the way (PLL,
    > DPLL or ADPLL).
    >
    > Also, a good reading about counters and digital synchronous design are
    > a very good starting points to understand the codes you may found
    > (IMHO, it is fundamental). Google for it!
    >
    > Regards,
    >
    > Rtafas
    >
    > wrote:
    >> Hello,
    >>
    >> I have a board with the Xilinx V2 Pro (xc2vp30). I am designing a BPSK
    >> demodulator on this board. For the demodulator, I need to generate
    >> arbitrary clock frequencies from 8 MHz to 10 MHz in 100 kHz increments
    >> from the base clock. How can I do this? Does anyone have any VHDL code
    >> I can use for this?
    >>
    >> Thanks and regards,
    >>
    >> Abhishek

    >
    Ian Muncaster, Jun 22, 2006
    #4
  5. pygmalion Guest

    Hello all,

    Thank you for the responses. For the time being, I've decided to use
    the DCMs on the FPGA I am using. However, I have a feeling I'll require
    more "arbitrary" clocks later into the project. Then, I am going to use
    some of the many suggestions I've received in this thread.

    Thanks and regards,

    Abhishek


    Ian Muncaster wrote:
    > Following on from Rtafas,
    > if your master clock is n*50khz then
    > you should be able to achieve a 50:50 duty cycle clock by loading a count
    > and a half count value then when counting if your below the half count out =
    > '1' and when above half count out = '0' this should achieve a near 50:50
    > duty cycle clock.
    >
    > Hope this is of help.
    >
    > REGARDS IAN.
    >
    > "Rtafas" <> wrote in message
    > news:...
    > > What is your master clock? If it is n*100khz, you may use a counter,
    > > the simplest way is count until you reach the "divider number -1" and
    > > generate an enable pulse. You will not get a 50% duty cycle clock (but
    > > you can count to generate it twice higher than you need and divide by
    > > two). The jitter will be the one from your oscilator.
    > >
    > > A DCO (or NCO) is good too, but only if jitter is not a problem (it is
    > > said that jitter is a master clock cycle plus the oscillator, but I
    > > have never found such calculations).
    > >
    > > Also, you may need to lock this clock, so, locked loop is the way (PLL,
    > > DPLL or ADPLL).
    > >
    > > Also, a good reading about counters and digital synchronous design are
    > > a very good starting points to understand the codes you may found
    > > (IMHO, it is fundamental). Google for it!
    > >
    > > Regards,
    > >
    > > Rtafas
    > >
    > > wrote:
    > >> Hello,
    > >>
    > >> I have a board with the Xilinx V2 Pro (xc2vp30). I am designing a BPSK
    > >> demodulator on this board. For the demodulator, I need to generate
    > >> arbitrary clock frequencies from 8 MHz to 10 MHz in 100 kHz increments
    > >> from the base clock. How can I do this? Does anyone have any VHDL code
    > >> I can use for this?
    > >>
    > >> Thanks and regards,
    > >>
    > >> Abhishek

    > >
    pygmalion, Jun 23, 2006
    #5
  6. Ricardo Guest

    DCM? fixed output then. Note that it has a minimun working frequency
    (about 1Mhz for Spartan3, if I am correct).

    If it's ok for your design, good then!

    Regards

    Tafas

    > Hello all,
    >
    > Thank you for the responses. For the time being, I've decided to use
    > the DCMs on the FPGA I am using. However, I have a feeling I'll require
    > more "arbitrary" clocks later into the project. Then, I am going to use
    > some of the many suggestions I've received in this thread.
    >
    > Thanks and regards,
    >
    > Abhishek
    >
    >
    > Ian Muncaster wrote:
    > > Following on from Rtafas,
    > > if your master clock is n*50khz then
    > > you should be able to achieve a 50:50 duty cycle clock by loading a count
    > > and a half count value then when counting if your below the half count out =
    > > '1' and when above half count out = '0' this should achieve a near 50:50
    > > duty cycle clock.
    > >
    > > Hope this is of help.
    > >
    > > REGARDS IAN.
    > >
    > > "Rtafas" <> wrote in message
    > > news:...
    > > > What is your master clock? If it is n*100khz, you may use a counter,
    > > > the simplest way is count until you reach the "divider number -1" and
    > > > generate an enable pulse. You will not get a 50% duty cycle clock (but
    > > > you can count to generate it twice higher than you need and divide by
    > > > two). The jitter will be the one from your oscilator.
    > > >
    > > > A DCO (or NCO) is good too, but only if jitter is not a problem (it is
    > > > said that jitter is a master clock cycle plus the oscillator, but I
    > > > have never found such calculations).
    > > >
    > > > Also, you may need to lock this clock, so, locked loop is the way (PLL,
    > > > DPLL or ADPLL).
    > > >
    > > > Also, a good reading about counters and digital synchronous design are
    > > > a very good starting points to understand the codes you may found
    > > > (IMHO, it is fundamental). Google for it!
    > > >
    > > > Regards,
    > > >
    > > > Rtafas
    > > >
    > > > wrote:
    > > >> Hello,
    > > >>
    > > >> I have a board with the Xilinx V2 Pro (xc2vp30). I am designing a BPSK
    > > >> demodulator on this board. For the demodulator, I need to generate
    > > >> arbitrary clock frequencies from 8 MHz to 10 MHz in 100 kHz increments
    > > >> from the base clock. How can I do this? Does anyone have any VHDL code
    > > >> I can use for this?
    > > >>
    > > >> Thanks and regards,
    > > >>
    > > >> Abhishek
    > > >
    Ricardo, Jun 23, 2006
    #6
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