assign constant to signal

Discussion in 'VHDL' started by supra, Apr 14, 2009.

  1. supra

    supra

    Joined:
    Apr 14, 2009
    Messages:
    1
    Hi,

    Why does in vhdl, it is able to read in multiples of four? It does not accept any other width for read/write?

    Thanks
    Last edited: Apr 14, 2009
    supra, Apr 14, 2009
    #1
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  2. supra

    JohnDuq

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    Dec 9, 2008
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    Constants aren't constrained, so you must be constrained elsewhere. A bit more detail on what you are attempting will be helpful.

    John
    JohnDuq, Apr 17, 2009
    #2
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