signal ram: ram_t := (others => (others '0'));

Discussion in 'VHDL' started by Travis, Jun 18, 2013.

  1. Travis

    Travis Guest

    I'm examining the VHDL for block and distributed ram on Xilinx, and a short google search led me to this site:
    http://vhdlguru.blogspot.com/2011/01/block-and-distributed-rams-on-xilinx.html

    The code I'm looking at is as follows:

    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;

    entity ram_example is
    port (Clk : in std_logic;
    address : in integer;
    we : in std_logic;
    data_i : in std_logic_vector(7 downto 0);
    data_o : out std_logic_vector(7 downto 0)
    );
    end ram_example;

    architecture Behavioral of ram_example is

    --Declaration of type and signal of a 256 element RAM
    --with each element being 8 bit wide.
    type ram_t is array (0 to 255) of std_logic_vector(7 downto 0);
    signal ram : ram_t := (others => (others => '0'));

    begin

    --process for read and write operation.
    PROCESS(Clk)
    BEGIN
    if(rising_edge(Clk)) then
    if(we='1') then
    ram(address) <= data_i;
    end if;
    data_o <= ram(address);
    end if;
    END PROCESS;

    end Behavioral;

    But I had a question about this part:
    signal ram : ram_t := (others => (others => '0'));

    I assume this is necessary because it helps the synthesizer make some optimizations and better infer LUTs or block ram, but I don't quite 'understand' it. I can parrot it in the meantime, but maybe someone out there has a good description?

    Thanks all,
    -Travis
    Travis, Jun 18, 2013
    #1
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  2. Travis

    Rob Gaddi Guest

    On Tue, 18 Jun 2013 11:20:38 -0700 (PDT)
    Travis <> wrote:

    > I'm examining the VHDL for block and distributed ram on Xilinx, and a short google search led me to this site:
    > http://vhdlguru.blogspot.com/2011/01/block-and-distributed-rams-on-xilinx.html
    >
    > The code I'm looking at is as follows:
    >
    > library IEEE;
    > use IEEE.STD_LOGIC_1164.ALL;
    >
    > entity ram_example is
    > port (Clk : in std_logic;
    > address : in integer;
    > we : in std_logic;
    > data_i : in std_logic_vector(7 downto 0);
    > data_o : out std_logic_vector(7 downto 0)
    > );
    > end ram_example;
    >
    > architecture Behavioral of ram_example is
    >
    > --Declaration of type and signal of a 256 element RAM
    > --with each element being 8 bit wide.
    > type ram_t is array (0 to 255) of std_logic_vector(7 downto 0);
    > signal ram : ram_t := (others => (others => '0'));
    >
    > begin
    >
    > --process for read and write operation.
    > PROCESS(Clk)
    > BEGIN
    > if(rising_edge(Clk)) then
    > if(we='1') then
    > ram(address) <= data_i;
    > end if;
    > data_o <= ram(address);
    > end if;
    > END PROCESS;
    >
    > end Behavioral;
    >
    > But I had a question about this part:
    > signal ram : ram_t := (others => (others => '0'));
    >
    > I assume this is necessary because it helps the synthesizer make some optimizations and better infer LUTs or block ram, but I don't quite 'understand' it. I can parrot it in the meantime, but maybe someone out there has a good description?
    >
    > Thanks all,
    > -Travis


    It's just declaring that the initial contents of the RAM should be all
    zeros. You can actually assign the initial values to be whatever you'd
    like.

    --
    Rob Gaddi, Highland Technology -- www.highlandtechnology.com
    Email address domain is currently out of order. See above to fix.
    Rob Gaddi, Jun 18, 2013
    #2
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  3. Travis

    GaborSzakacs Guest

    Rob Gaddi wrote:
    > On Tue, 18 Jun 2013 11:20:38 -0700 (PDT)
    > Travis <> wrote:
    >
    >> I'm examining the VHDL for block and distributed ram on Xilinx, and a short google search led me to this site:
    >> http://vhdlguru.blogspot.com/2011/01/block-and-distributed-rams-on-xilinx.html
    >>
    >> The code I'm looking at is as follows:
    >>
    >> library IEEE;
    >> use IEEE.STD_LOGIC_1164.ALL;
    >>
    >> entity ram_example is
    >> port (Clk : in std_logic;
    >> address : in integer;
    >> we : in std_logic;
    >> data_i : in std_logic_vector(7 downto 0);
    >> data_o : out std_logic_vector(7 downto 0)
    >> );
    >> end ram_example;
    >>
    >> architecture Behavioral of ram_example is
    >>
    >> --Declaration of type and signal of a 256 element RAM
    >> --with each element being 8 bit wide.
    >> type ram_t is array (0 to 255) of std_logic_vector(7 downto 0);
    >> signal ram : ram_t := (others => (others => '0'));
    >>
    >> begin
    >>
    >> --process for read and write operation.
    >> PROCESS(Clk)
    >> BEGIN
    >> if(rising_edge(Clk)) then
    >> if(we='1') then
    >> ram(address) <= data_i;
    >> end if;
    >> data_o <= ram(address);
    >> end if;
    >> END PROCESS;
    >>
    >> end Behavioral;
    >>
    >> But I had a question about this part:
    >> signal ram : ram_t := (others => (others => '0'));
    >>
    >> I assume this is necessary because it helps the synthesizer make some optimizations and better infer LUTs or block ram, but I don't quite 'understand' it. I can parrot it in the meantime, but maybe someone out there has a good description?
    >>
    >> Thanks all,
    >> -Travis

    >
    > It's just declaring that the initial contents of the RAM should be all
    > zeros. You can actually assign the initial values to be whatever you'd
    > like.
    >


    For _most_ Xilinx FPGA famlies, the bitstream initializes all memories
    by default. If you don't specify a value to initialize the RAMs, then
    it will be all zeroes in the bitstream. This also helps to reduce
    bitstream size when using compression. Explicitly choosing all zeroes,
    when you really don't care about the initial value has the effect
    of making simulation match the hardware.

    If instead you wanted to make sure you don't read uninitialized memory
    and rely on its value, I've seen something like:

    signal ram : ram_t := (others => (others => 'U'));

    --
    Gabor
    GaborSzakacs, Jun 18, 2013
    #3
  4. Travis

    Andy Guest

    While the explicit 'U' initialization may be more readable (which is generally an admirable goal), it is not necessary.

    Per the LRM and the type definition, ram is initialized to (others => (others => 'U')) unless explicitly initialized otherwise.

    Andy
    Andy, Jun 19, 2013
    #4
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