Assignment to output signal from internal signal not istantaneous

Discussion in 'VHDL' started by dibacco73, Feb 10, 2009.

  1. dibacco73

    dibacco73

    Joined:
    Feb 10, 2009
    Messages:
    1
    I have the following code snippet:

    entity driver is
    port
    (
    clk_o : out std_logic
    );
    end driver;
    --
    architecture rtl of driver is
    begin
    signal i_clk : std_logic :='0';
    i_clk <= NOT i_clk AFTER 100ns;
    clk_o <= i_clk;

    clk_o is delayed respect to i_clk, is this possible?

    Thank you,
    Antonio.
     
    dibacco73, Feb 10, 2009
    #1
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  2. dibacco73

    joris

    Joined:
    Jan 29, 2009
    Messages:
    152
    Yes, clk_o is assigned a "delta" period of time after i_clk. It's by design of VHDL.
    You can get around this by using a proces instead (making i_clk a variable instead of a signal)
     
    joris, Feb 12, 2009
    #2
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