Assignment to output signal from internal signal not istantaneous

[dibacco73]

I have the following code snippet:

entity driver is
port
(
clk_o : out std_logic
);
end driver;
--
architecture rtl of driver is
begin
signal i_clk : std_logic :='0';
i_clk <= NOT i_clk AFTER 100ns;
clk_o <= i_clk;

clk_o is delayed respect to i_clk, is this possible?

Thank you,
Antonio.

 

[joris]

Yes, clk_o is assigned a "delta" period of time after i_clk. It's by design of VHDL.
You can get around this by using a proces instead (making i_clk a variable instead of a signal)