signal assignment and Delta delay

[Roya]

Hi,
can any one help me about this , the following signal assignment is in the process:

Red<=dout;
temp <= temp-"00000001";
Green<=dout;
temp <= temp-"00000001";
Blue<=dout;
temp <= temp-"00000001";

i want to read this three Red ,Green and Blue in the duration of just one clock through the rom which i got from the xilinx ipcores . but as you see after i change the signal "temp" that is bound to the address of the rom ,simultaneously I want to read the signal "dout" thar is bound to output of the rom. I have no choice , i understand the Delta-delay concept but ,I have no choice , i must read these three consecutive rows of the rom at the same time. how can i do it? how can I manipulate the address and I read the row that the manipulated address points to?



**********signal declaration*********
signal temp: std_logic_vector(7 downto 0);
signal dout : std_logic_vector(7 downto 0);
signal Red : std_logic_vector(7 downto 0);
signal Green : std_logic_vector(7 downto 0);
*******************************************


************component declaration************

component rom
port(
clk:in std_logic;
addr:in std_logic_vector(7 downto 0);
dout ut std_logic_vector(7 downto 0));
end component;
******************************************


**********component configuration********
memory_instance: rom
port map(
clk=>clk,
addr=>temp,
dout => dout);
************************************

I appreciate so much if U could help me.

sincerely
Roya

 

[allsey_1987]

mmm... i think you might need to do some reading on VHDL...

You do realise for every iteration of a process a signal can only be assigned to once. and this assignment doesn't take effect until the next time the process is triggered right?

if your hardware needs to work in different ways at a particular time your best approach is to use a state machine and counter which is calibrated to the clock speed...

 

[allsey_1987]

i think what you want to do is this:

signal RED : std_logic_vector(7 downto 0);
signal GREEN : std_logic_vector(7 downto 0);
signal BLUE : std_logic_vector(7 downto 0);

signal Counter: std_logic_vector(1 downto 0);

readFromRom: process(clock)
begin
	if(rising_edge(clock)) then
		case currentAddr is
			when "00" =>
				RED <= dout;
			when "01" =>
				GREEN <= dout;
			when "10" =>
				BLUE <= dout;
			when others =>
				null;
		end case
		temp <= temp-"00000001";
		if(currentAddr = "10") then
			currentAddr <= "00";
		else
			currentAddr <= currentAddr + 1;
	end if;
end process readRomRom;

 

[Roya]

First i want to thank you so much since you give me a pluperfect and quaint point(state machine) .you're right, i need to do some reading on VHDL. I am a beginner in VHDL and I'm going to learn it professionally
Second , I have a question again : these three assignments happen at 3 rising edge of clock, am i right? as you said "in every iteration of a process a signal can only be assigned to once" so they can't be initialized and shouldn't have been initialized at one clock, right? so a part of my problem is still remaining:
"I can not read them at one clock" , such these problems are not resolved in VHDL, Are they?

God speed you

 

[Roya]

I understood that these simultaneous assignments are not possible so i try another way: I make the clk, 3 times faster .so when rising edge of the faster clk is comming for the third time , all the signals Red,Blue and Green are initialized and all of them are prepared , at this time the sysclk goes to the rising edge mode so the other modules start their works as before with the frequency 27 Mhz.
am i right?
but i face this error --> "ERROR:Xst:841:"bad condition in wait statement, or only one clock per process."
because of this part of my code in my top module during the post-route simulation:
***********in my top module:**************
sysclkGeneratorrocess
begin
sysclk<='0';
for count in 1 to 3 loop
wait until clk'event and clk ='1';
end loop;
sysclk <= '1';
wait;
end process sysclkGenerator;

*******************************************


*****************in my testbench :*****************

clk<=not(clk) after 3.08 ns ;


*****************************************************

actualy the frequency of sysclk should be 27 Mhz, means 18.5 ns one and 18.5 ns zero, so sysclk is 6*3.08=18.5