basic question about data types

Discussion in 'VHDL' started by Martin Sauer, Dec 1, 2008.

  1. Martin Sauer

    Martin Sauer Guest

    Hi,

    I have some basic question about data types in vhdl. I hope you can give
    me an answer. Which library should I use in new designs (numeric_std or
    std_logic_unsigned)? The unsigned type is a vector type?

    Thank your for your answer.

    bye

    martin sauer
     
    Martin Sauer, Dec 1, 2008
    #1
    1. Advertising

  2. Martin Sauer

    Martin Sauer Guest

    Hi,

    I have an example:

    In my VHDL code I have two unsigned signals

    signal sDataR : unsigned (9 downto 0);
    signal sR : unsigned (1 downto 0);

    I want to add bit 1 of sR to sDataR. sDataR + sR(1) doesn't work. I will
    get the following error:

    ERROR: cannot convert type std_ulogic to type unsigned

    How can I add one bit of an unsigned signal to another unsigned signal?

    Thank you for your answer.

    bye

    martin sauer

    Martin Sauer schrieb:
    > Hi,
    >
    > I have some basic question about data types in vhdl. I hope you can give
    > me an answer. Which library should I use in new designs (numeric_std or
    > std_logic_unsigned)? The unsigned type is a vector type?
    >
    > Thank your for your answer.
    >
    > bye
    >
    > martin sauer
     
    Martin Sauer, Dec 1, 2008
    #2
    1. Advertising

  3. Martin Sauer

    Tricky Guest

    On 1 Dec, 08:00, Martin Sauer <> wrote:
    > Hi,
    >
    > I have an example:
    >
    > In my VHDL code I have two unsigned signals
    >
    > signal sDataR : unsigned (9 downto 0);
    > signal sR : unsigned (1 downto 0);
    >
    > I want to add bit 1 of sR to sDataR. sDataR + sR(1) doesn't work. I will
    > get the following error:
    >
    > ERROR: cannot convert type std_ulogic to type unsigned
    >
    > How can I add one bit of an unsigned signal to another unsigned signal?
    >
    > Thank you for your answer.
    >
    > bye
    >
    > martin sauer
    >
    > Martin Sauer schrieb:
    >
    > > Hi,

    >
    > > I have some basic question about data types in vhdl. I hope you can give
    > > me an answer. Which library should I use in new designs (numeric_std or
    > > std_logic_unsigned)? The unsigned type is a vector type?

    >
    > > Thank your for your answer.

    >
    > > bye

    >
    > > martin sauer

    >
    >


    Definatly use numeric_std, because it is an actual IEEE standard,
    std_logic_unsigned is not - it was origionally defined by Synopsys and
    compiled (wrongly) in to the IEEE library. Different vendors implement
    std_logic_unsigned differently, whereas the IEEE defined numeric_std.

    As for your error, sR(1) is just a single bit, which is why you're
    getting the problem. Addition has to be done on 2 unsigned numbers
    that have the same length that match the result length. So, the best
    way around your problem:

    signal output : unsigned(10 downto 0); --addition output will be 1
    bit bigger than largest input if you dont want overflow
    ...
    output <= ('0' & sDataR) + resize(sR, output'length);
    --'0' is concatenated the make sDataR 11 bits.

    if you really wanted to add a single bit from sR then you have to use
    a range to keep it as an unsigned type. Indexing just 1 returns a
    std_ulogic, as you found.:

    output <= ('0' & sDataR) + resize(sR(1 downto 1), output'length);
     
    Tricky, Dec 1, 2008
    #3
  4. Martin Sauer

    olekk Guest

    Martin Sauer wrote:
    > Hi,
    >
    > I have an example:
    >
    > In my VHDL code I have two unsigned signals
    >
    > signal sDataR : unsigned (9 downto 0);
    > signal sR : unsigned (1 downto 0);
    >
    > I want to add bit 1 of sR to sDataR. sDataR + sR(1) doesn't work. I will
    > get the following error:
    >
    > ERROR: cannot convert type std_ulogic to type unsigned
    >
    > How can I add one bit of an unsigned signal to another unsigned signal?
    >
    > Thank you for your answer.
    >
    > bye
    >
    > martin sauer
    >
    > Martin Sauer schrieb:
    > > Hi,
    > >
    > > I have some basic question about data types in vhdl. I hope you can give
    > > me an answer. Which library should I use in new designs (numeric_std or
    > > std_logic_unsigned)? The unsigned type is a vector type?
    > >


    operator '+' is defined in std_logic_unsigned for logic vectors. So
    you can do it like

    use ieee.std_logic_unsigned;
    .....
    srout <= sDataR + sR(1 downto 1);

    It will certainly compile

    Regards
     
    olekk, Dec 1, 2008
    #4
  5. Martin Sauer

    Tricky Guest


    > operator '+' is defined in std_logic_unsigned for logic vectors. So
    > you can do it like
    >



    See above 2 posts
     
    Tricky, Dec 1, 2008
    #5
  6. Martin Sauer

    Martin Sauer Guest

    Hi all,

    thank you for your fast answer.

    Now it works fine.

    bye

    martin sauer

    olekk schrieb:
    >
    > Martin Sauer wrote:
    >> Hi,
    >>
    >> I have an example:
    >>
    >> In my VHDL code I have two unsigned signals
    >>
    >> signal sDataR : unsigned (9 downto 0);
    >> signal sR : unsigned (1 downto 0);
    >>
    >> I want to add bit 1 of sR to sDataR. sDataR + sR(1) doesn't work. I will
    >> get the following error:
    >>
    >> ERROR: cannot convert type std_ulogic to type unsigned
    >>
    >> How can I add one bit of an unsigned signal to another unsigned signal?
    >>
    >> Thank you for your answer.
    >>
    >> bye
    >>
    >> martin sauer
    >>
    >> Martin Sauer schrieb:
    >>> Hi,
    >>>
    >>> I have some basic question about data types in vhdl. I hope you can give
    >>> me an answer. Which library should I use in new designs (numeric_std or
    >>> std_logic_unsigned)? The unsigned type is a vector type?
    >>>

    >
    > operator '+' is defined in std_logic_unsigned for logic vectors. So
    > you can do it like
    >
    > use ieee.std_logic_unsigned;
    > ....
    > srout <= sDataR + sR(1 downto 1);
    >
    > It will certainly compile
    >
    > Regards
     
    Martin Sauer, Dec 1, 2008
    #6
  7. Martin Sauer a écrit :
    > Hi all,
    >
    > thank you for your fast answer.
    >
    > Now it works fine.


    The quick and ugly way. Read the other answers please. Please. I
    *really* mean it.

    Nicolas
     
    Nicolas Matringe, Dec 1, 2008
    #7
    1. Advertising

Want to reply to this thread or ask your own question?

It takes just 2 minutes to sign up (and it's free!). Just click the sign up button to choose a username and then you can ask your own questions on the forum.
Similar Threads
  1. Kevin
    Replies:
    1
    Views:
    446
    Wibble
    Jun 12, 2005
  2. Paras Sharma

    basic data types

    Paras Sharma, Aug 12, 2003, in forum: C++
    Replies:
    1
    Views:
    297
    John Harrison
    Aug 12, 2003
  3. ramu
    Replies:
    2
    Views:
    332
    rlblaster
    Feb 20, 2006
  4. Gary Roach
    Replies:
    0
    Views:
    117
    Gary Roach
    Sep 1, 2013
  5. Fábio Santos
    Replies:
    0
    Views:
    129
    Fábio Santos
    Sep 4, 2013
Loading...

Share This Page