baudrate generator

[kiran423]

sir,
when i was synthesing the baud rate generator code it was giving one error as
"generic(clock_in_speed, clock_out_speed: integer);"
error:
line 25: Generic <clock_in_speed> has not been given a value.

please helpme and give reply to my id:[email protected]
and what is code for test bench for baud rate generator
please helpme it is urgent

 

[jeppe]

Try this

generic( clock_in_speed: integer := 9600;
clock_out_speed: integer := 9600);"

Your welcome

 

[kiran423]

thanks for reply

sir,
i was using baudrate generator for multichannel uart.so,i need to apply diffferent baud rates as
"generic(clock_in_speed, clock_out_speed: integer);"
you are given only one baud rate=9600;
with this line we can use for for different baud rates as 2400,4600 etc?????????
please give reply
and what is test bench for baud rate generator???????.
iam in urgent need of complete code for multichannel uart using fifo techinique.
please please help me i has to submit on next tuesday.
please help me
please.

 

[joris]

With one generic value you can have only one constant.

In general, to have multiple possible generic values, one could instantiate multiple instances with different values, and add logic to select the right one (if that doesn't end up being too big)

I obviously don't know enough to tell whether that applies here, though

 

[jeppe]

Hi

Try this -> esd.cs.ucr.edu/labs/uart/uart.html

Copy to the addressline of the Browser

 

[kiran423]

request please

sir,
i need complete vhdl or verilog code for multichannel uart controller using fifo .
please help me .
it is urgent i have to submit on tuesday.
please help me

 

[kiran423]

i need test bench for baud rate generator need to simulate in xilinx
please help me

 

[jeppe]

How does your code look like?
If you use the xilinx ISE tool can you simply add a new source .. testbench

 

[kiran423]

same synthesis code is added for test bench?
iam using xilinx ise 9.2i
please provide complete code and test bench for multichannel uart controller using fifo techinique

 

[kiran423]

Library IEEE;
Use ieee.std_logic_1164.all;
Use ieee.numeric_std.all;
Entity topmodule is
Port (
Clk : in std_logic;
Uartout : out std_logic; -----9600
Uartout2: out std_logic; ------4800
Uartout3: out std_logic-----2400//;
);
End topmodule;

Architecture beav of topmodule is
Constant speed: natural: = 50e6;// here error is there Line 33. parse error, unexpected COLON, expecting AFFECT or SEMICOLON
Signal clk1: std_logic;
Signal clk_s: std_logic;
Signal clk_s1: std_logic;
Signal uartout: std_logic;// ERROR Line 37. Redeclaration of symbol uartout.
Component uart1
Generic (constant system_speed: natural: = 50e6; integer);ERROR IS Line 39. parse error, unexpected COLON, expecting SEMICOLON or CLOSEPAR
Port (clock: in std_logic;
Txd: out std_logic);
End component;
Begin
P1: process (clk)
Begin
If (clk'event and clk = '1') then
Clk_s <= not (clk_s);
End if;
End process P1;

P2: process (clk)
Begin
If (clk_s'event and clk_s = '1') then
Clk_s1 <= not (clk_s1);
End if;
End process P2;

Clock_mana1: uart1 generic map (system_speed=> speed)
Port map (clk, uartout);
Clock_mana2: uart1 generic map (system_speed=> speed)
Port map (clk_s, uartout2);
Clock_mana3: uart1 generic map (system_speed=> speed
Port map (clk_s1, uartout3);
End beav;

Line 33. parse error, unexpected COLON, expecting AFFECT or SEMICOLON

Line 37. Redeclaration of symbol uartout.

Line 39. parse error, unexpected COLON, expecting SEMICOLON or CLOSEPAR


PLEASE HELP ME ITS URGENT