baudrate generator

Discussion in 'VHDL' started by kiran423, Mar 28, 2011.

  1. kiran423

    kiran423

    Joined:
    Mar 28, 2011
    Messages:
    7
    sir,
    when i was synthesing the baud rate generator code it was giving one error as
    "generic(clock_in_speed, clock_out_speed: integer);"
    error:
    line 25: Generic <clock_in_speed> has not been given a value.

    please helpme and give reply to my id:ravikirangot@yahoo.co.in
    and what is code for test bench for baud rate generator
    please helpme it is urgent
     
    kiran423, Mar 28, 2011
    #1
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  2. kiran423

    jeppe

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    Try this

    generic( clock_in_speed: integer := 9600;
    clock_out_speed: integer := 9600);"

    Your welcome
     
    jeppe, Mar 28, 2011
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  3. kiran423

    kiran423

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    Mar 28, 2011
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    thanks for reply

    sir,
    i was using baudrate generator for multichannel uart.so,i need to apply diffferent baud rates as
    "generic(clock_in_speed, clock_out_speed: integer);"
    you are given only one baud rate=9600;
    with this line we can use for for different baud rates as 2400,4600 etc?????????
    please give reply
    and what is test bench for baud rate generator???????.
    iam in urgent need of complete code for multichannel uart using fifo techinique.
    please please help me i has to submit on next tuesday.
    please help me
    please.
     
    kiran423, Mar 30, 2011
    #3
  4. kiran423

    joris

    Joined:
    Jan 29, 2009
    Messages:
    152
    With one generic value you can have only one constant.

    In general, to have multiple possible generic values, one could instantiate multiple instances with different values, and add logic to select the right one (if that doesn't end up being too big)

    I obviously don't know enough to tell whether that applies here, though
     
    joris, Mar 30, 2011
    #4
  5. kiran423

    jeppe

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    Location:
    Denmark
    Hi

    Try this -> esd.cs.ucr.edu/labs/uart/uart.html

    Copy to the addressline of the Browser
     
    jeppe, Mar 31, 2011
    #5
  6. kiran423

    kiran423

    Joined:
    Mar 28, 2011
    Messages:
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    request please

    sir,
    i need complete vhdl or verilog code for multichannel uart controller using fifo .
    please help me .
    it is urgent i have to submit on tuesday.
    please help me
     
    kiran423, Mar 31, 2011
    #6
  7. kiran423

    kiran423

    Joined:
    Mar 28, 2011
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    i need test bench for baud rate generator need to simulate in xilinx
    please help me
     
    kiran423, Apr 5, 2011
    #7
  8. kiran423

    jeppe

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    How does your code look like?
    If you use the xilinx ISE tool can you simply add a new source .. testbench
     
    jeppe, Apr 5, 2011
    #8
  9. kiran423

    kiran423

    Joined:
    Mar 28, 2011
    Messages:
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    same synthesis code is added for test bench?
    iam using xilinx ise 9.2i
    please provide complete code and test bench for multichannel uart controller using fifo techinique
     
    kiran423, Apr 10, 2011
    #9
  10. kiran423

    kiran423

    Joined:
    Mar 28, 2011
    Messages:
    7
    Library IEEE;
    Use ieee.std_logic_1164.all;
    Use ieee.numeric_std.all;
    Entity topmodule is
    Port (
    Clk : in std_logic;
    Uartout : out std_logic; -----9600
    Uartout2: out std_logic; ------4800
    Uartout3: out std_logic-----2400//;
    );
    End topmodule;

    Architecture beav of topmodule is
    Constant speed: natural: = 50e6;// here error is there Line 33. parse error, unexpected COLON, expecting AFFECT or SEMICOLON
    Signal clk1: std_logic;
    Signal clk_s: std_logic;
    Signal clk_s1: std_logic;
    Signal uartout: std_logic;// ERROR Line 37. Redeclaration of symbol uartout.
    Component uart1
    Generic (constant system_speed: natural: = 50e6; integer);ERROR IS Line 39. parse error, unexpected COLON, expecting SEMICOLON or CLOSEPAR
    Port (clock: in std_logic;
    Txd: out std_logic);
    End component;
    Begin
    P1: process (clk)
    Begin
    If (clk'event and clk = '1') then
    Clk_s <= not (clk_s);
    End if;
    End process P1;

    P2: process (clk)
    Begin
    If (clk_s'event and clk_s = '1') then
    Clk_s1 <= not (clk_s1);
    End if;
    End process P2;

    Clock_mana1: uart1 generic map (system_speed=> speed)
    Port map (clk, uartout);
    Clock_mana2: uart1 generic map (system_speed=> speed)
    Port map (clk_s, uartout2);
    Clock_mana3: uart1 generic map (system_speed=> speed
    Port map (clk_s1, uartout3);
    End beav;

    Line 33. parse error, unexpected COLON, expecting AFFECT or SEMICOLON

    Line 37. Redeclaration of symbol uartout.

    Line 39. parse error, unexpected COLON, expecting SEMICOLON or CLOSEPAR


    PLEASE HELP ME ITS URGENT
     
    kiran423, Apr 17, 2011
    #10
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