bcd-7segment decoder

Discussion in 'VHDL' started by arthur merlo, Jun 15, 2012.

  1. arthur merlo

    arthur merlo Guest

    Hi guys, I'm new in VHDL and would be glad if anyone could help me
    with
    my bcd-7segments decoder. I dont know why its not compiling

    LIBRARY ieee;
    USE ieee.std_logic_1164.all;
    ENTITY decod_7seg IS
    PORT (
    a : IN STD_LOGIC_VECTOR(17 DOWNTO 0);
    HEX0 : OUT STD_LOGIC_VECTOR(6 DOWNTO 0)
    );
    END decod_7seg;
    ARCHITECTURE behaviour OF decod_7seg IS
    BEGIN


    HEX0 <= "1000000";
    when a="0000"
    else
    HEX0 <= "1111001";
    when a="0001"
    else
    HEX0<= "0100100";
    when a="0010"
    else
    HEX0<= "0110000";
    when a="0011"
    else
    HEX0 <= "0011001";
    when a="0100"
    else
    HEX0<= "0100010";
    when a="0101"
    else
    HEX0 <= "0000010";
    when a="0110"
    else
    HEX0 <= "1111000";
    when a="0111"
    else
    HEX0 <= "0000000";
    when a="1000"
    else
    HEX0 <= "0010000";
    when a="1001"


    END behaviour;
     
    arthur merlo, Jun 15, 2012
    #1
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  2. arthur merlo

    KJ Guest

    On Thursday, June 14, 2012 8:19:31 PM UTC-4, Arthur Merlo wrote:
    > Hi guys, I'm new in VHDL and would be glad if anyone could help me
    > with
    > my bcd-7segments decoder. I dont know why its not compiling
    >
    > LIBRARY ieee;
    > USE ieee.std_logic_1164.all;
    > ENTITY decod_7seg IS
    > PORT (
    > a : IN STD_LOGIC_VECTOR(17 DOWNTO 0);
    > HEX0 : OUT STD_LOGIC_VECTOR(6 DOWNTO 0)
    > );
    > END decod_7seg;
    > ARCHITECTURE behaviour OF decod_7seg IS
    > BEGIN
    >
    >
    > HEX0 <= "1000000";
    > when a="0000"
    > else
    > HEX0 <= "1111001";
    > when a="0001"

    <snip>
    > else
    > HEX0 <= "0010000";
    > when a="1001"
    >
    >


    The correct form is
    HEX0 <= "1000000"
    when a="0000"
    else
    "1111001"
    when a="0001"
    else
    ....

    Also, if you're planning on turning this into hardware, you need to end thestatement without the final condition like this...

    "0000000" when a="1000"
    else "0010000"; -- when a="1001"

    Get rid of the last conditional check. If you don't you'll be defining something that gets implemented as a form of latch which in programmable devices is generally a 'no-no'. Just from a logic perspective, ask yourself what should be the output if the input does not match any of the expected inputs? You have to output something, so choose it. That is the value to use on the final 'else' without any additional 'when a= ...' conditions.

    Kevin Jennings
     
    KJ, Jun 15, 2012
    #2
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  3. arthur merlo <> wrote:
    > Hi guys, I'm new in VHDL and would be glad if anyone could help me
    > with
    > my bcd-7segments decoder. I dont know why its not compiling


    You should look at the syntax specification of concurrent assignments again.

    It's _one_ assignment, i.e. _one_ signal assignment operator '<=' and _one_
    semicolon.

    Try something like this:

    HEX0 <= "1000000" when a = "0000" else
    "1111001" when a = "0001" else
    "0100100" when a = "0010" else
    "0110000" when a = "0011" else
    "0011001" when a = "0100" else
    "0100010" when a = "0101" else
    "0000010" when a = "0110" else
    "1111000" when a = "0111" else
    "0000000" when a = "1000" else
    "0010000" when a = "1001" else
    "-------";

    Enrik
     
    Enrik Berkhan, Jun 15, 2012
    #3
  4. arthur merlo wrote:

    > Hi guys, I'm new in VHDL and would be glad if anyone could help me
    > with
    > my bcd-7segments decoder. I dont know why its not compiling
    >
    > LIBRARY ieee;
    > USE ieee.std_logic_1164.all;
    > ENTITY decod_7seg IS
    > PORT (
    > a : IN STD_LOGIC_VECTOR(17 DOWNTO 0);
    > HEX0 : OUT STD_LOGIC_VECTOR(6 DOWNTO 0)
    > );
    > END decod_7seg;


    Besides the other two replies you already got: input 'a' needs to be 4 bits
    wide: 3 DOWNTO 0. The values you compare with are 4 bits wide.

    --
    Paul Uiterlinden
    www.aimvalley.nl
     
    Paul Uiterlinden, Jun 18, 2012
    #4
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