Behiovar simulation of FF

[sridar]

Hi all,

Why the behavior simulation of flip flop doesn't shows any delay (I use xilinx isim)? Input appears at the output at the same clock edge.

 

[eliascm]

Simulation of FF Shows No Delay

In order for the simulation to show delays the model for the FF must have the delays built in. If you are doing a timing simulation using the vendor's post synthesis model then the delays should show up. For a functional simulation using your VHDL code no delays will show up unless you have delays built in to your design which is not likely.