Bidirectional (bus) delay help needed

Discussion in 'VHDL' started by Nicolas Matringe, Sep 23, 2004.

  1. Hi all
    I have a VME bus model to which I would like to add backplane delays
    between modules.
    The problem is that most signals are bidirectional (as in every bus) and
    I don't know how to model this:

    Module A Module B Module C
    X ---A to B--> X ---B to C--> X (at time T1, X driven by module A)
    X <--B to A--- X ---B to C--> X (at time T2, X driven by module B)

    Any help is welcome :eek:)
    --
    ____ _ __ ___
    | _ \_)/ _|/ _ \ Adresse de retour invalide: retirez le -
    | | | | | (_| |_| | Invalid return address: remove the -
    |_| |_|_|\__|\___/
    Nicolas Matringe, Sep 23, 2004
    #1
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  2. Hi Nicolas,

    Regarding a very similar problem I found some information in the
    archives of this newsgroup. In short: VHDL doesn't have a simple way
    to model transmission (or transfer) gates (which would be the keywords
    to search for).

    However, a while back, someone posted a general description (IIRC, the
    code he was referring to was copyrighted) of an algorithm to obtain
    the desired behavior using a `postponed' process.

    I never bothered to dig deeper into that matter since a) I was
    restricted to VHDL'87 (in 2003!) and b) in my particular case, since I
    was really only interested in one end of the transfer gate, it was
    possible to simplify the problem to using a hardcoded data-eye and
    home-brewn bidirectional buffer models instead of the ones from tha
    ASIC library.

    Hope that helps,
    Marcus
    Marcus Harnisch, Sep 27, 2004
    #2
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  3. Marcus Harnisch a écrit:
    > Hi Nicolas,
    >
    > Regarding a very similar problem I found some information in the
    > archives of this newsgroup. In short: VHDL doesn't have a simple way
    > to model transmission (or transfer) gates (which would be the keywords
    > to search for).


    Right, I found interesting posts in the NG archives.


    > However, a while back, someone posted a general description (IIRC, the
    > code he was referring to was copyrighted) of an algorithm to obtain
    > the desired behavior using a `postponed' process.


    I found a link to some code written by Ben Cohen. Looks very interesting.



    > Hope that helps,


    Yes it does :eek:)
    Thanks a lot


    --
    ____ _ __ ___
    | _ \_)/ _|/ _ \ Adresse de retour invalide: retirez le -
    | | | | | (_| |_| | Invalid return address: remove the -
    |_| |_|_|\__|\___/
    Nicolas Matringe, Sep 28, 2004
    #3
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