Marco said:
My name is Marco and I'm working on my final year project, one subblock of
my project is a fft.
I would like to develope it myself (the fft) , but their is no time for that
because i have only 12 weeks for the hole project.
I got the cf_fft 512(vhdl version) on opencores.org but i have problems with
it,
the only thing that i get on the output_0_o is zero!
Is their a special pattern that i have to plug in at the three control
inputs
(enable_i,reset_i,sync_i<= i tested all 8 pattern) or do i need a special
clock ???
It would be very nice of you to give me a short introduction what i have
to do to bring the fft to run.
Greetings Marco
You have the source code (and probably some documentation), then you should
probably read it and try to understand how it works (big lines at least).
And simulation will let you actually "see" it work, though automatically
generated code isn't great for this...
Don't forget that FFTs are deep memories. In other words, they have a large
latency, by construct.
You may try to inject some noise (random values are good for that), run for
sufficient length, and check that you have "something" coming out after a while.
Then, you may inject a sinewave + noise, and see that you see the proper bin
standing out. etc...
Be ready to handle complex numbers (I/Q pairs).
Hint : you can use math_real in your test bench to generate the stimuli.
Hardware DSP is fun.
If you don't like the confluence version, you may go for a more traditional
radix-4 and radix-2 based approach. (I think it's what cf does generate anyway)
I don't like this code very much, especially the unsigned(0 downto 0) for the
control signals which is just an unnecessary pain. But it's free.
You need a pulse on sync_i to start the FFT calculation, some random data on the
inputs, and some (well many) clock cycles to see data coming out.
----
Just tried it : it works. You have a latency of ~2610 clock cycle.
(512 points FFT from the archive name)
The stimulus for the pins you ask for is trivial :
signal done : boolean;
constant Period : time := 10 ns;
begin
Reset <= '1', '0' after Period;
Clock <= '0' when done else not Clock after Period / 2;
Enable <= '1';
Sync_in <= '0', '1' after 4 * period, '0' after 5 * Period;
Done <= true after 4096 * Period;
For the data, as i said, you can use the UNIFORM function as a random nbr generator.
The output is "UUUU.....UUU" until sync_out goes up, followed by the data.
My complete test bench is just about 60 lines.
It's an 1/2 hour effort to get the source and make it produce some data...
but I think you should invest a little time in understanding how hardware
FFTs are implemented, the various ways to do it with respective advantages, etc...
In a final year project, I guess the idea is to learn as much as possible,
and using the confluence FFT (really a black box) probably won't teach you a lot.
But that's my view of it.
FFTs are probably becoming like multipliers : nobody cares anymore how they are
built internally, provided that they work as expected...
On FPGA targets, I would rather use the vendor's macros, which are now
nearly unbeatable in most cases.
Bert Cuzeau
