clock multiplication

[patrick.melet]

hi everybody,

I would like to do a clock multiplcation.

My idea was to count how many samples I have in one period of the
original clock. Latch the last value of this counter : so I've got the
number of sample into one period of the clock.

Then I create a second counter which count toward the number of sample
compute last and now with this counter I can create a second clock.

CLK1 : 111111000000111111000000
counter 1 : 012345012345012345
Max counter : 5 5 5
counter 2 : 012345012345012345
CLK2: 111000111000111000

My VHDL is :

if top_baud='1' then
compteur_baud_max <= count_1;
count_1 <= 0;
else
count_1 <= count_1 + 1;
end if;

if count_2<compteur_bit_max then
count_2<= count_2+ 1;
else
count_2<= 0;
compteur_bit_max <= compteur_baud_max;
end if;


if (count_2 <= compteur_bit_max/4) or (count_2 > compteur_bit_max/2 and
count_2 <= 3*compteur_bit_max/4) then
clock_bit <= '1';
else
clock_bit <= '0';
end if;

My original clock1 has non constant period and the period varies....
So I've got problem in this clock generation

thanks if you have ideas

 

[Isaac Bosompem]

hi everybody,

I would like to do a clock multiplcation.

My idea was to count how many samples I have in one period of the
original clock. Latch the last value of this counter : so I've got the
number of sample into one period of the clock.

Then I create a second counter which count toward the number of sample
compute last and now with this counter I can create a second clock.

CLK1 : 111111000000111111000000
counter 1 : 012345012345012345
Max counter : 5 5 5
counter 2 : 012345012345012345
CLK2: 111000111000111000

My VHDL is :

if top_baud='1' then
compteur_baud_max <= count_1;
count_1 <= 0;
else
count_1 <= count_1 + 1;
end if;

if count_2<compteur_bit_max then
count_2<= count_2+ 1;
else
count_2<= 0;
compteur_bit_max <= compteur_baud_max;
end if;


if (count_2 <= compteur_bit_max/4) or (count_2 > compteur_bit_max/2 and
count_2 <= 3*compteur_bit_max/4) then
clock_bit <= '1';
else
clock_bit <= '0';
end if;

My original clock1 has non constant period and the period varies....
So I've got problem in this clock generation

thanks if you have ideas

Why not use a clock manager in the FPGA to take care of the job? Or are
making one to be simulated not synthesized?

 

[patrick.melet]

hello,

what do you mean by clock manager... I would like to use a PLL but on
Stratix Altera FPGA, there is a minimum input clock frequency of about
15 MHz, and my clocks are under 4 MHz